Fujitsu Microelectronics Speeds Design Closure of 10 Million Gate ASIC With Sequence

SANTA CLARA, Calif.--(BUSINESS WIRE)--March 26, 2002--Sequence Design, Inc. announced today that it has teamed with Fujitsu Microelectronics America, Inc. (FMA) in a joint development program to speed design closure of a 10 million gate, 200MHz networking ASIC for a leading customer.

"With tight time-to-market pressures for our customers, we need tools like Sequence's PhysicalStudio to take our designers out of the design-iteration loop and move them to tapeout," said Tetsu Tanizawa, Fujitsu's director of worldwide design. "Our joint development with Sequence helped us achieve our complex, high-performance design objectives in record time."

Sequence's PhysicalStudio(TM) optimizes chip timing and signal integrity issues concurrently, both before and after routing. It is fully interoperable with industry-standard routing tools, permitting existing physical design flows to reach fast, predictable SoC design closure in silicon geometries below 180 nanometers.

Fujitsu's 10 million gate, 180-nanometer ASIC for a leading networking company contains complex, high-speed modules in an array fashion, a design that introduced many routing-congestion and wire-delay challenges at the top level. To free up more channels for the top level routing, the modules are packed into a very tight footprint, resulting in a highly congested layout. With the existing tools, this design often results in numerous iterations on the path to design closure. By adding PhysicalStudio, Fujitsu achieved design closure under this remarkably congestive condition for the two most difficult modules (which cover 80 percent of the chip area), while delivering a 30 percent improvement in timing.

"Using PhysicalStudio's full-context, post-route optimization, Fujitsu achieved its most challenging design closure and validated the need for physical optimization," said Vic Kulkarni, chief operating officer for Sequence. "Fujitsu, like many of our major customers, is now moving other designs toward closure with PhysicalStudio and experiencing similar results. They are meeting or beating their specs, and doing it in record time. We will continue to provide them with the leading-edge physical design technology needed to get the job done."

About PhysicalStudio

PhysicalStudio allows system-on-chip designers to:

• reach 35 percent higher clock speeds
• achieve a 5 percent to 15 percent reduction in power over traditional physical design flows
• compensate for signal integrity effects, such as crosstalk-induced "setup" violations, "hold" violations and functional "glitch" errors
• accurately predict and immunize against noise during placement
• surgically correct timing and signal-integrity issues "along the route" using a patent-pending FullContext(TM)post-route technique

By unifying placement-driven optimization and post-route optimization into a single engine, the product ensures that every net in a design is correctly driven and all timing and signal integrity violations are eliminated. PhysicalStudio operates on large, hierarchical designs with varying abstractions at the top-level such as register-bounded blocks, STAMP, LIB and CLF.

About SoC Design Closure

Silicon processing technology below 180 nanometers creates chips offering unprecedented performance combined with low power consumption. However, existing physical design methodologies and tools have difficulty delivering on this potential, because of complex interactions between the logic and interconnect in the chip. As designers struggle to achieve timing convergence, they invariably encounter schedule delays. The analysis-based optimization solutions offered by Sequence achieve the power and signal integrity goals set during the architectural stages of a design and thereby eliminate schedule delays. SoC design closure solutions from Sequence drop seamlessly into existing design flows, protecting previous tool investment while reducing time-to-market. Sequence Design is the first EDA company to focus comprehensively on SoC design closure, from the architectural handoff all the way through logical and physical implementation and final verification.

About Sequence

Sequence Design, Inc., the SoC Design Closure Company(SM), enables system-on-chip designers to bring higher-performance and lower-power integrated circuits quickly to tapeout. Sequence's physical design software and solutions give its more than 100 customers the competitive advantage they need to excel in aggressive technology markets, despite demanding complexity and time-to-market issues of sub-180 nanometer design.

Sequence has worldwide development and field service operations. The company was formed through the merger of Sente, Inc., Sapphire Design Automation, Inc. and Frequency Technology. Sequence is privately held. Sequence is a member of Cadence Design Systems' Connections(TM)and Mentor Graphics' Open Door(TM) partnership programs.

Additional information on the company can be found at sequencedesign.com.

Note to Editors: All trademarks mentioned herein are the property of their respective owners.

     lochpr
     Public Relations for Sequence Design Inc.
     Jim Lochmiller, 541/552-0616
     lochpr@yahoo.com